The present disclosure relates generally to information handling systems (IHSs), and more particularly to a hardware based processor performance state (P-state) control system for an IHS.
As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option is an information handling system (IHS). An IHS generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes. Because technology and information handling needs and requirements may vary between different applications, IHSs may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in IHSs allow for IHSs to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, IHSs may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
IHS processors generally operate at a number of different operating states defined under an Advanced Configuration and Power Interface (ACPI) specification. These different states relate generally to power states, such as global states (G0-G3), system states (S0-S5), device states (D0-D3), processor states (C0-C3) and performance states (P0-Pn). Processor P-state changes are traditionally controlled by software algorithms running on a host processor. Systems for adjusting processor P-states generally run on a periodic basis (e.g., approximately every 30 to 60 milliseconds) to limit displacing actual work producing code execution on the processor. This, in-turn, minimizes the effectiveness that these programs have on improving processor performance.
Applications, such as office type applications, and some video processing tasks do not task the processor very heavily. Accordingly, this allows the processor to enter and spend most of its time in low power sleep states. In these low power sleep states, the processor dissipates less power than in the active states. But, in these low power sleep states, the processor is unable to execute code. The processor exits these sleep states due to interrupts, bus master activity or more often due to system timer tick interrupts, which typically occur every 15 milliseconds.
The Business Applications Performance Corporation (BAPCo) is a central consortium of IHS developers that develops objective performance benchmarking standards for testing IHS performance using different operating systems and different software applications. Two such performance benchmark systems are MobileMark and SysMark. Traces ran on MobileMark and SysMark applications, which run on a suite of office worker-type applications, allow the processor to spend up to 80% or more of its time in low power sleep states.
Investigations have shown that over 90% of the time when the processor enters an active state, it stays in this active state for a very short period of time (e.g., <˜5 milliseconds) before returning to a sleep state. As such, this provides multiple problems for the effectiveness of the P-state adjustment. For example, most of the time that the P-state algorithm runs, a P-state change is not required. Thus, running this code uses unnecessary resources and power. In another example, when a relatively large work load occurs it is likely to be “bursty”, needing a lot of processing for a very short period of time. However, the execution duty cycle causes a time delay in executing the P-state change, and thus, the delay misses some of the effective time where the P-state change would have effected performance.
Accordingly, it would be desirable to provide an improved processor P-state control system for an IHS.